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Serial Mesh Backplane PICMG2.20 Rev1.0
650-CPSM11WL


■Features
  1. PICMG2. 20 Standard (serial mesh bus) is designed according to the bus standard which is fully compliant to data communication between multiple protocols, where the serial mesh fabric of the full mesh bus connection is additionally assigned to the CPCI platform.
  2. The ZD connector (high speed differential connector) is used in the P4 Area so as to enable 2.5Gbps transfer rate with the SERDES driver which is defined as the fabric interface between the accurate differential impedance control of the backplane and the module board.
  3. Backplane is composed with 11 slots (CPCI bus) and the serial mesh bus (P4) is composed of 8 slots (Slot 4 to Slot 11), and supports 8 channels x 2 ports (Smaller Replicated Mesh specification).
　 　


Specifications
CPCI Bus 11 slots, 64-bit data bus (PCI to PCI bridge board mounted)
Serial mesh bus (P4)　　　　 8 slots (from Slot 4 to Slot 11)
Packaged connectors
Pl、P2、P3、P5 2mm HM connectors
P4（Slot 1 to Slot 3） 2mm HM connector
P4（Slot 4 to Slot 11） ZD connector
Substrate specification
Number of layers 14 layers
Thickness 4.5mm
Material CCL-HL950K（Low relative permittivity material）
Specific permittivity 3.5
Predetermined impedance
CPCI bus Zo＝65Ω±10％
Serdes transmission line Zdiff＝100Ω±10％
Auxiliary clock line Zo＝50Ω±10％
Multi-drop differential clock line Zdiff＝130Ω±10％
（terminator with　80Ω）

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